As processor units that accomplish intended processes, CPUs (Central Processing Units) are known. Among them, parallel computing devices composed of array type processors in which a plurality of processors are arranged in an array shape for miniaturization and high performance (refer to Patent documents 1 to 6 that follow) are known. The related arts presented in these Patent documents are hereinafter referred to as the first related art.
A technique that generates a program that operates on a parallel computing device according to the first related art (this program is also referred to as an object code) is presented in the following Patent document 7. This program generation technique is hereinafter referred to as the second related art.
The parallel computing device according to the first related art executes a process based on an object code. The object code contains at least one entry of configuration information generated based on data to be processed. Configuration information is information that serves to virtually configure a circuit in a parallel computing device and is composed of computation instructions that are issued to individual computing units that accomplish parallel processes of the parallel computing device and information that represents relationships of connections of individual computing units.
Each entry of configuration information is stored in a memory of the parallel computing device and identified by a number assigned thereto (this number is hereinafter referred to as the configuration number). In the parallel computing device, virtual circuits are configured based on designated entries of configuration information and processes are executed by the circuit.
The first related art employs a technique in which a process is executed by directly designating the configuration number. For example, the configuration number that is an address of the memory is designated.
In addition, according to the first related art, the current status of the parallel computing device corresponds to an entry of configuration information that is currently being executed. Status numbers corresponding to individual configuration numbers stored in the parallel computing device have been defined and the entry of configuration information that is currently being executed is managed with a status number.
Moreover, the first related art employs a technique in which a next transition status number and a configuration number are selected from a status transition table.
The status transition table correlates a status number that represents an entry of configuration information that is currently being executed (this status number is hereinafter referred to as the current status number) with an event signal that is generated as a computation result by a circuit that is realized based on the entry of configuration information corresponding to the current status number so as to define a status number and a configuration number to be selected next. Referring to the status transition table, a status number and a configuration number to be selected next can be obtained based on the current status number and the event signal.
An object code is composed of both a plurality of entries of configuration information based on which the parallel computing device executes a intended process and the status transition table.
Generally, since a configuration number is defined for each object code, if a plurality of objects are tried to be installed to one parallel computing device according to the first related art, the configuration numbers of these object codes may overlap and thereby individual entries of configuration information cannot be uniquely identified.
In this case, if a plurality of object codes is converted into one object code, such overlaps may be prevented from occurring. However, if a plurality of object codes is converted into one object code such that configuration numbers do not overlap, the number of configuration numbers of the converted object code becomes the sum of the number of configuration numbers of individual object codes.
In the parallel computing device according to the first related art, each entry of configuration information stored in the parallel computing device is selected by directly designating a configuration number and thereby a large object code that uses configuration information whose number of entries exceeds the number that can be stored in the parallel computing device cannot be realized.
In contrast, a parallel computing device employing the technique disclosed in the following Patent document 8 has been proposed by the applicant of the present patent application. This technique will be hereinafter referred to as the third related art.
The parallel computing device according to the third related art employs a technique in which a configuration number is designated indirectly, not directly. In this related art, a number in which a configuration number is directly designated is referred to as a physical number, whereas a number in which a configuration number is indirectly designated is referred to as a logical number. According to the third related art, a configuration number is designated as a logical number and the logical number is converted into a physical number so as to identify an entry of configuration information.
Specifically, a logical number is contained in an object code, whereas a physical number is managed in the parallel computing device. More specifically, a configuration number contained in an object code is a logical configuration number. In addition, a configuration number managed in the parallel computing device such as a configuration number of an entry of configuration information that is currently being executed is a physical configuration number.
According to the third related art, since the parallel computing device is provided with means that converts a logical configuration number into a physical configuration number, configuration information whose number of entries exceeds those that can be stored in the parallel computing device can be designated as a logical number. As a result, large object codes can be used for the parallel computing device.
(PATENT DOCUMENTS)
Patent document 1: Japan Patent No. 3576837
Patent document 2: Japan Patent No. 3444216
Patent document 3: Japan Patent No. 3269526
Patent document 4: Japan Patent No. 3616518
Patent document 5: Japan Patent No. 3674515
Patent document 6: Japan Patent No. 3528922
Patent document 7: Japan Patent No. 3921367
Patent document 8: International Laid-Open No. WO 2007/114059A1